In modern high density memories, such as random access memories having 2.sup.20 bits (1 Megabit) or more, the time and equipment required to test functionality and timing of all bits in the memory constitutes a significant portion of the manufacturing cost. Accordingly, as the time required for such testing increases, the manufacturing costs also increase. Similarly, if the time required for the testing of the memory can be reduced, the manufacturing cost of the memories is similarly reduced. Since the manufacturing of memory devices is generally done in high volume, the savings of even a few seconds per device can result in significant cost reduction and capital avoidance, considering the high volume of memory devices produced.
Random access memories (RAMs) are especially subject to having significant test costs, not only because of the necessity of both writing data to and reading data from each of the bits in the memory, but also because RAMs are often subject to failures due to pattern sensitivity. Pattern sensitivity failures arise because the ability of a bit to retain its stored data state may depend upon the data states stored in, and the operations upon, bits which are physically adjacent to a particular bit being tested. This causes the test time for RAMs to be not only linearly dependent upon its density (i.e, the number of bits available for storage) but, for some pattern sensitivity tests, dependent upon the square (or 3/2 power) of the number of bits. Obviously, as the density of RAM devices increases (generally by a factor of four, from generation to generation), the time required to test each bit of each device in production increases at a rapid rate.
It should be noted that many other integrated circuit devices besides memory chips themselves utilize memories on-chip. Examples of such integrated circuits include many modern microprocessors and microcomputers, as well as custom devices such as gate arrays which have memory embedded therewithin. Similar cost pressures are faced in the production of these products as well, including the time and equipment required for testing of the memory portions.
A solution which has been used in the past to reduce the time and equipment required for the testing of semiconductor memories such as RAMs is the use of special "test" modes, where the memory enters a special operation different from its normal operation. In such test modes, the operation of the memory can be quite different from that of normal operation, as the operation of internal testing can be done without being subject to the constraints of normal operation.
An example of a special test mode is an internal "parallel", or multi-bit, test mode. Conventional parallel test modes allow access to more than one memory location in a single cycle, with common data written to and read from the multiple locations simultaneously. For memories which have multiple input/output terminals, multiple bits would be accessed in such a mode for each of the input/output terminals, in order to achieve the parallel test operation. This parallel test mode of course is not available in normal operation, since the user must be able to independently access each bit in order to utilize the full capacity of the memory. Such parallel testing is preferably done in such a way so that the multiple bits accessed in each cycle are physically separated from one another, so that there is little likelihood of pattern sensitivity interaction among the simultaneously accessed bits. A description of such parallel testing may be found in McAdams et al., "A 1-Mbit CMOS Dynamic RAM With Design-For-Test Functions", IEEE Journal of Solid-State Circuits, Vol SC-21, No. 5 (October 1986), pp. 635-642.
Other special test modes may be available for particular memories. Examples of tests which may be performed in such modes include the testing of memory cell data retention times, tests of particular circuits within the memory such as decoders or sense amplifiers, and the interrogation of certain portions of the circuit to determine attributes of the device such as whether or not the memory has had redundant rows or columns enabled. The above-referenced article by McAdams et al. describes these and other examples of special test functions.
Of course, when the memory device is in such a special test mode, it is not operating as a fully randomly accessible memory. As such, if the memory is in one of the test modes by mistake, for example when installed in a system, data cannot be stored and retrieved as would be expected for such a memory. For example, when in parallel test mode, the memory writes the same data state to a plurality of memory locations. Accordingly, when presented with an address in parallel test mode, the memory will output a data state which does not depend solely on the stored data state, but may also depend upon the results of the parallel comparison. Furthermore, the parallel test mode necessarily reduces the number of independent memory locations to which data can be written and retrieved, since four, or more, memory locations are simultaneously accessed. It is therefore important that the enabling of the special test modes be accomplished in such a manner that the chance is low that a special test mode will be inadvertently entered.
Prior techniques for entry into special test mode include the use of a special terminal for indicating the desired operation. A simple prior technique for the entry into test mode is the presentation of a logic level, high or low, at a dedicated terminal to either select the normal operation mode or a special test mode such as parallel test, as described in U.S. Pat. No. 4,654,849. Another approach for the entry into test mode using such a dedicated terminal is disclosed in Shimada et al., "A 46-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, (Feb. 1988) pp. 53-58, where a test mode is enabled by the application of a high voltage to a dedicated control pad while performing a write operation. These techniques are relatively simple but they of course require an additional terminal besides those necessary for normal memory operation. While such an additional terminal may be available when the memory is tested in wafer form, significant test time also occurs after packaging, during which special test modes are also useful. In order to use this technique of a dedicated test enable terminal for package test, it is therefore necessary that the package have a pin or other external terminal for this function. Due to the desires of the system designer that the circuit package be as small as possible, with as few connections as possible, the use of a dedicated pin for test mode entry is therefore undesirable. Furthermore, if a dedicated terminal for entering the test mode is provided in packaged form, the user of the memory must take care to ensure that the proper voltage is presented to this dedicated terminal so that the test mode is not unintentionally entered during system usage.
Another technique for enabling special test modes is the use of an overvoltage signal at one or more terminals which have other purposes during normal operation, such overvoltage indicating that the test mode is to be enabled, such as is also described in U.S. Pat. No. 4,654,849, and in U.S. Pat. No. 4,860,259 (using an overvoltage on an address terminal). Said U.S. Pat. No. 4,860,259 also describes a method which enables a special test mode in a dynamic RAM responsive to an overvoltage condition at the column address strobe terminal, followed by the voltage on this terminal falling to a low logic level. The McAdams et al. article cited hereinabove, describes a method of entering test mode which includes the multiplexing of a test number onto address inputs while an overvoltage condition exists on a clock pin, where the number at the address inputs selects one of several special test modes. Such overvoltage enabling of special test modes, due to its additional complexity, adds additional security that special test modes will not be entered inadvertently, relative to the use of a dedicated control terminal for enabling the test modes.
However, the use of an overvoltage signal at a terminal, where that terminal also has a function during normal operation, still is subject to inadvertent enabling of the special mode. This can happen during "hot socket" insertion of the memory, where the memory device is installed into a location which is already powered up. Depending upon the way in which the device is physically placed in contact with the voltages, it is quite possible that the terminal at which an overvoltage enables test mode is biased to a particular voltage before the power supply terminals are so biased. The overvoltage detection circuit conventionally used for such terminals compares the voltage at the terminal versus a power supply or other reference voltage. In a hot socket insertion, though, the voltage at the terminal may be no higher than the actual power supply voltage, but may still enable the special mode if the terminal sees this voltage prior to seeing the power supply voltage that the terminal is compared against. Accordingly, even where special test modes are enabled by an overvoltage signal at a terminal, a hot socket condition may still inadvertently enable the special mode.
It should also be noted that similar types of inadvertent enabling of special test modes can occur during power up of the device, if the transients in the system are such that a voltage is presented to the terminal at which an overvoltage selects the test mode, prior to the time that the power supply voltage reaches the device. Furthermore, due to the random nature in which internal nodes of the device can power-up, many prior devices can power up in the special test mode even without the presentation of such signals.
The inadvertent test mode entry is especially dangerous where a similar type of operation is required to disable the test mode. For example, the memory described in the McAdams et al. article requires an overvoltage condition, together with a particular code, to return to normal operation from the test mode. In the system context, however, there may be no way in which an overvoltage can be applied to the device (other than the hot socket or power up condition that inadvertently placed the device in test mode). Accordingly, in such a system, if the memory device is in test mode, there may be no way short of powering down the memory in which normal operation of the memory may be regained.
It is therefore an object of this invention to provide an improved circuit and method for inhibiting the enabling of a special mode in an integrated circuit device during power-up of the device after a brief power-down event.
In addition, it should be noted that conventional power-on reset circuits are used in the art for the control of certain operations other than entry into test mode in a device until power-up is achieved. It has been found that such circuits may not reset in the event of brief losses of power, so that upon return of the power supply to its nominal voltage, the power-on reset function is lost.
It is therefore a further object of this invention to provide an improved circuit and method which resets quickly in the event of loss of power supply voltage, so that inhibition of circuit functions during power-up is effected after such brief power losses.
Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to this specification together with its drawings.